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K4H560838D-TCB3 Datasheet 256Mb D-die DDR Sdram

Manufacturer: Samsung Semiconductor

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Overview

256Mb Key.

Key Features

  • Double-data-rate architecture; two data transfers per clock cycle.
  • Bidirectional data strobe(DQS).
  • Four banks operation.
  • Differential clock inputs(CK and CK).
  • DLL aligns DQ and DQS transition with CK transition.
  • MRS cycle with address key programs -. Read latency 2, 2.5 (clock) www. DataSheet4U. com -. Burst length (2, 4, 8) -. Burst type (sequential & interleave).
  • All inputs except data & DM are sampled at the positive going edge of.

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