K4C89183AF
Description
K4C89183AF is a CMOS Double Data Rate Network-DRAM containing 301,989,888 memory cells. K4C89183AF is organized as 4,194,304-words x 4 banks x18 bits.
Key Features
- Fully Synchronous Operation
- Double Data Rate (DDR)
- Data input/output are synchronized with both edges of DS / QS
- Differential Clock (CLK and CLK) inputs
- CS, FN and all address input signals are sampled on the positive edge of CLK
- Output data (DQs and QS) is aligned to the crossings of CLK and CLK. Fast clock cycle time of 3.0 ns minimum
- Clock : 333 MHz maximum
- Data : 666 Mbps/pin maximum Quad Independent Banks operation Fast cycle and Short Latency Uni-directional Data Strobe Distributed Auto
