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K4S280432D - 128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL

Description

The K4S280432C is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 4 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Features

  • JEDEC standard 3.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4 & 8 ) -. Burst type (Sequential & Interleave).
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst read single-bit write operation.
  • DQM for masking.
  • Auto & self refresh.
  • 64ms refresh period (4K Cycle) CMOS SD.

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Other Datasheets by Samsung Semiconductor

Part Number Description
K4S280432A 128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL
K4S280432B 128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL
K4S280432C 128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL
K4S280432E 128Mb E-die SDRAM Specification
K4S280432E-TC75 128Mb E-die SDRAM Specification

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com K4S280432D CMOS SDRAM 128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL Rev. 0.1 Sept. 2001 * Samsung Electronics reserves the right to change products or specification without notice. Rev.0.1 Sept. 2001 K4S280432D CMOS SDRAM Revision History Revision 0.0 (Mar., 2001) Revision 0.1 (Sep., 2001) • • Redefined IDD1 & IDD4 in DC Characteristics Changed the Notes in Operating AC Parameter. < Before > 5. For 1H/1L, tRDL=1CLK and tDAL=1CLK+tRP is also supported . SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. < After > 5.In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. Rev.0.1 Sept.
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