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K4Y50084UC - (K4Y50024UC - K4Y50164UC) 512Mbit XDR TM DRAM

Download the K4Y50084UC datasheet PDF (K4Y50024UC included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for (k4y50024uc - k4y50164uc) 512mbit xdr tm dram.

Description

The timing diagrams in Figure 1 illustrate XDR DRAM device write and read transactions.

There are three sets of pins used for normal memory access transactions: CFM/CFMN clock pins, RQ11..0 request pins, and DQ15..0/DQN15..0 data pins.

Features

  • Highest pin bandwidth available - 4000/3200/2400 Mb/s Octal Data Rate(ODR) Signaling.
  • Bi-directional differential RSL(DRSL) - Flexible read/write bandwidth allocation - Minimum pin count.
  • On-chip termination - Adaptive impedance matching - Reduced system cost and routing complexity.
  • Highest sustained bandwidth per DRAM device - Up to 8000 MB/s sustained data rate - Eight banks : bank-interleaved transaction at full bandwidth - Dynamic request scheduling - Ear.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (K4Y50024UC_Samsungsemiconductor.pdf) that lists specifications for multiple related part numbers.

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Full PDF Text Transcription

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www.DataSheet4U.com K4Y50164UC K4Y50084UC K4Y50044UC K4Y50024UC XDRTM DRAM 512Mbit XDR TM DRAM(C-die) Revision 1.1 August 2006 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2.
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