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K6R4008V1B - 512K x8 Bit High Speed Static RAM

General Description

The K6R4008V1B is a 4,194,304-bit high-speed Static Random Access Memory organized as 524,288 words by 8 bits.

The K6R4008V1B uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle.

Key Features

  • Fast Access Time 10,12,15ns(Max. ).
  • Low Power Dissipation Standby (TTL) : 50mA(Max. ) (CMOS) : 10mA(Max. ) 1.2mA(Max. )- L-Ver. Operating K6R4008V1B-10 : 205mA(Max. ) K6R4008V1B-12 : 200mA(Max. ) K6R4008V1B-15 : 195mA(Max. ).
  • Single 3.3 ±0.3V Power Supply.
  • TTL Compatible Inputs and Outputs.
  • Fully Static Operation - No Clock or Refresh required.
  • Three State Outputs.
  • 2V Minimum Data Retention ; L-Ver. only.
  • Center Power/Ground Pin C.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com PRELIMINARY CMOS SRAM K6R4008V1B-C/B-L, K6R4008V1B-I/B-P Document Title 512Kx8 Bit High Speed Static RAM(3.3V Operating). Operated at Commercial and Industrial Temperature Ranges. Revision History Rev No. Rev. 0.0 Rev. 1.0 History Initial release with Design Target. Release to Preliminary Data Sheet. 1.1. Replace Design Target to Preliminary. Release to Final Data Sheet. 2.1. Delete Preliminary. 2.2. Add 30pF capacitive in test load. 2.3. Relax DC characteristics. Item Previous ICC 10ns 170mA 12ns 160mA 15ns 150mA ISB f=max. 40mA ISB1 f=0 10 / 1mA IDR VDR=3.0V 0.9mA Draft Data Jan. 1st, 1997 Jun. 1st, 1997 Remark Design Target Preliminary Rev. 2.0 Feb.11th.1998 Final Current 205mA 200mA 195mA 50mA 10 / 1.2mA 1.0mA Jun.27th 1998 Final Rev. 2.