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K7D321874C Datasheet 1Mx36 & 2Mx18 SRAM

Manufacturer: Samsung Semiconductor

Overview: K7D323674C K7D321874C 1Mx36 & 2Mx18 SRAM 36Mb DDR SRAM Specification 153BGA with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. www.DataSheet4U.com * Samsung Electronics reserves the right to change products or specification without notice. -1- Rev. 1.0 August 2006 K7D323674C K7D321874C Document Title 36M DDR SYNCHRONOUS SRAM 1Mx36 & 2Mx18 SRAM Revision History Rev No. Rev. 0.0 Rev. 0.1 Rev. 0.2 Rev. 1.0 History Initial document. Change AC Characteritics, Pin Capacitance, DC Characteristics Change Samsung JEDEC Code in ID REGISTER DEFINITION Correct Typo Draft Data Nov. 2005 Apr. 2006 Jun. 2006 Aug. 2006 Remark Advance Preliminary Preliminary Final www.DataSheet4U.com -2- Rev. 1.

Download the K7D321874C datasheet PDF. This datasheet also includes the K7D323674C variant, as both parts are published together in a single manufacturer document.

Key Features

  • 1Mx36 or 2Mx18 Organizations. 1.8~2.5V VDD/1.5V ~1.8VDDQ. HSTL Input and Outputs. Single Differential HSTL Clock. Synchronous Pipeline Mode of Operation with Self-Timed Late Write.
  • Free Running Active High and Active Low Echo Clock Output Pin.
  • Registered Addresses, Burst Control and Data Inputs. 1Mx36 & 2Mx18 SRAM.
  • Registered Outputs.
  • Double and Single Data Rate Burst Read and Write.
  • Burst Count.