K7Q161864B - (K7Q161864B / K7Q163664B) 512Kx36 & 1Mx18 QDR TM b4 SRAM

Samsung semiconductor

The K7Q161864B by Samsung semiconductor is a (K7Q161864B / K7Q163664B) 512Kx36 & 1Mx18 QDR TM b4 SRAM. Below is the official datasheet preview.

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K7Q161864B (K7Q161864B / K7Q163664B) 512Kx36 & 1Mx18 QDR TM b4 SRAM by Samsung semiconductor - Datasheet Preview — Official preview page of the **K7Q161864B** (K7Q161864B / K7Q163664B) 512Kx36 & 1Mx18 QDR TM b4 SRAM datasheet (Samsung semiconductor).

Datasheet Details

Part number	K7Q161864B
Manufacturer	Samsung semiconductor
File Size	370.30 KB
Description	(K7Q161864B / K7Q163664B) 512Kx36 & 1Mx18 QDR TM b4 SRAM
Datasheet	K7Q161864B_Samsungsemiconductor.pdf
Additional preview pages of the K7Q161864B datasheet.

K7Q161864B Product details

Description

Input Clock Input Clocks for Output data Address Inputs Data Inputs Data Outputs Write Control Read Control Byte Write Control Input Reference Voltage Output Driver Impedance Control Power Supply ( 2.5V ) Output Power Supply ( 1.5V or 1.8V ) Ground JTAG Test Mode Select JTAG Test Data Input JTAG Test Clock JTAG Test Data Output No Connect 3 2 1 NOTES Notes: 1. C, C, K or K cannot be set to VREF voltage.2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it

Features

1.8V/2.5V +0.1V/-0.1V Power Supply.
I/O Supply Voltage 1.5V +0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.
Separate independent read and write data ports with concurrent read and write operation.
HSTL I/O.
Full data coherency, providing most current data.
Synchronous pipeline read with self timed late write.
Registered address, control and data input/output.
DDR(Double Data Rate) Interface on read and write.

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K7Q163654A - (K7Q161854A / K7Q163654A) 1Mx18-bit QDR SRAM

Published: Mar 23, 2007 |