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KM44C16000B, KM44C16100B
CMOS DRAM
16M x 4bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 16,777,216 x 4 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory
cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time(-45, -5 or -6), package type(SOJ or TSOP-II) are optional fea-
tures of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. This 16Mx4 Fast
Page Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption
and high reliability.
FEATURES
• Part Identification
- KM44C16000B(5.0V, 8K Ref.)
- KM44C16100B(5.0V, 4K Ref.)
• Active Power Dissipation
Speed
-45
-5
-6
8K
550
495
440
Unit : mW
4K
715
660
605
• Refresh Cycles
Part
NO.
KM44C16000B*
KM44C16100B
Refresh
cycle
8K
4K
Refresh time
Normal
64ms
* Access mode & RAS only refresh mode
: 8K cycle/64ms
CAS-before-RAS & Hidden refresh mode
: 4K cycle/64ms
• Performance Range
Speed tRAC
tCAC
-45 45ns 12ns
-5 50ns 13ns
-6 60ns 15ns
tRC
80ns
90ns
110ns
tPC
31ns
35ns
40ns
• Fast Page Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Fast parallel test mode capability
• TTL(5.0V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• +5.0V±10% power supply
FUNCTIONAL BLOCK DIAGRAM
RAS
CAS
W
Control
Clocks
VBB Generator
Vcc
Vss
Refresh Timer
Refresh Control
Refresh Counter
A0~A12
(A0~A11)*1
A0~A10
(A0~A11)*1
Row Address Buffer
Col. Address Buffer
Note) *1 : 4K Refresh
Row Decoder
Memory Array
16,777,216 x 4
Cells
Column Decoder
Data in
Buffer
Data out
Buffer
DQ0
to
DQ3
OE
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
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