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KS88C01424 - (KS88C01416 - KS88C01424) KS88 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU

This page provides the datasheet information for the KS88C01424, a member of the KS88C01416 (KS88C01416 - KS88C01424) KS88 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU family.

Datasheet Summary

Description

Pin Names P0.0

P0.7 Pin Type I/O Pin Description I/O port with bit-programmable pins.

Configurable to input or push-pull output mode.

Pull-up resistors are assignable by software.

Features

  • include:.
  • Efficient register-oriented architecture.
  • Selectable CPU clock sources.
  • Idle and Stop power-down mode release by interrupt.
  • Built-in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to specific interrupt levels. KS88C01416/C01424.

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Datasheet preview – KS88C01424

Datasheet Details

Part number KS88C01424
Manufacturer Samsung semiconductor
File Size 294.83 KB
Description (KS88C01416 - KS88C01424) KS88 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU
Datasheet download datasheet KS88C01424 Datasheet
Additional preview pages of the KS88C01424 datasheet.

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Other Datasheets by Samsung semiconductor
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  • KS88C0116 - 8-Bit CMOS Microcontroller

Full PDF Text Transcription

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KS88C01416/P01416/C01424/P01424 (Preliminary Spec) PRODUCT OVERVIEW 1 www.DataSheet4U.com PRODUCT OVERVIEW KS88-SERIES MICROCONTROLLERS Samsung's KS88 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals and various mask-programmable ROM sizes. Important CPU features include: — Efficient register-oriented architecture — Selectable CPU clock sources — Idle and Stop power-down mode release by interrupt — Built-in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to specific interrupt levels.
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