KS88C01624 - (KS88C01524 - KS88C01632) 8-bit single-chip CMOS microcontrollers

This page provides the datasheet information for the KS88C01624, a member of the KS88C01524 (KS88C01524 - KS88C01632) 8-bit single-chip CMOS microcontrollers family.

Datasheet Summary

Description

of 44-QFP and 42-SDIP Pin Names P0.0

P0.7 Pin Type I/O Pin Description I/O port with bit-programmable pins.

Configurable to input or push-pull output mode.

Pull-up resistors can be assigned by software.

Features

include:.
Efficient register-oriented architecture.
Selectable CPU clock sources.
Idle and Stop power-down mode release by interrupt.
Built-in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to specific interrupt levels. S3C80F7/C80F9/C80G7/C80G9 Microcontroll.

Samsung semiconductor

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Datasheet Details

Part number	KS88C01624
Manufacturer	Samsung semiconductor
File Size	226.83 KB
Description	(KS88C01524 - KS88C01632) 8-bit single-chip CMOS microcontrollers
Datasheet	KS88C01624 Datasheet
Additional preview pages of the KS88C01624 datasheet.

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Other Datasheets by Samsung semiconductor

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KS88C01016 - (KS88C01004 - KS88C01116) KS88 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU
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Full PDF Text Transcription

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S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) PRODUCT OVERVIEW 1 www.DataSheet4U.com PRODUCT OVERVIEW S3C8-SERIES MICROCONTROLLERS Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include: — Efficient register-oriented architecture — Selectable CPU clock sources — Idle and Stop power-down mode release by interrupt — Built-in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to specific interrupt levels.

Published: Jul 9, 2008 |