E 0
*…T5 90% 0
*…T7 0
*…T6 0
*…T8 10% DATA GND 10% MOD 2V
*…Tmod GND 10% 10% Note 7-1
*z DCLK,SPL,SPR,LBR,LP,PS,REV,R0
*`
*y Note 7-2
*.

of SHARP's devices and are not intended to guarantee any circuit design or permit any industrial property right or other.

Power supply of gate driver(high level) Remarks Pin No. 40 41 42 43 44 45 46 47 48 49 50 Symbol AGND AGND REV COM AGND AGND AGND AGND AGND AGND AGND I/O
*|
*| I O
*|
*|
*|
*|
*|
*|
*| Ground(Analog) reverse cont.

LQ035Q7DB03

LQ035Q7DB02

LQ035Q7DB02R

LQ035Q7DB05

LQ035Q7DB06

LQ035Q7DH01

LQ035Q7DH02

LQ035Q7DH02F

LQ035Q7DH03

LQ035Q7DH06

LQ035Q7DH07

LQ035Q1DH01

LQ035Q3DG01