LH540204 Description
The LH540204 is a FIFO (First-In, First-Out) memory device, based on fully-static CMOS dual-port SRAM technology, capable of storing up to 4096 nine-bit words. It follows the industry-standard architecture and package pinouts for nine-bit asynchronous FIFOs. Each nine-bit LH540204 word may consist of a standard eight-bit byte, together with a parity bit or a block-marking/framing bit.
LH540204 Key Features
- Fast Access Times: 20/25/35/50 ns
- Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology
- Input Port and Output Port Have Entirely Independent Timing
- Expandable in Width and Depth
- Full, Half-Full, and Empty Status Flags
- Data Retransmission Capability
- TTL-patible I/O
- Pin and Functionally patible with Sharp LH5499 and with Am/IDT/MS7204
- Control Signals Assertive-LOW for Noise Immunity
- Packages: 28-Pin, 300-mil PDIP 28-Pin, 300-mil SOJ