LH5496 Datasheet | Sharp Corporation

FEATURES - Fast Access Times: 15 - /20/25/35/50/65/80 ns - Full CMOS Dual Port Memory Array - Fully Asynchronous Read and Write - Expandable-in Width and Depth - Full, Half-Full, and Empty Status Flags - Read Retransmit Capability - TTL patible I/O - Packages: 28-Pin, 300-mil PDIP 28-Pin, 600-mil PDIP 32-Pin PLCC - Pin and Functionally patible with IDT7201 FUNCTIONAL DESCRIPTION The LH5496/96H are dual port memories with internal addressing to implement a First-In, First-Out algorithm. Through an advanced dual port architecture, they provide fully asynchronous read/write operation. Empty, Full, and Half-Full status flags are provided to prevent data overflow and underflow. In addition, internal logic provides for unlimited expansion in both word size and depth. Read and write operations automatically access sequential locations in memory in that data is read out in the same order that it was written, that is on a First-In, First-Out basis. Since the address sequence is internally predefined, no external address information is required for the operation of this device. A ninth data bit is provided for parity or control information often needed in munication applications. Empty, Full, and Half-Full status flags monitor the extent to which data has been written into the FIFO, and prevent improper operations (i.e., Read if the FIFO is empty, or Write if the FIFO is full). A retransmit feature resets the Read address pointer to its initial position, thereby allowing repetitive readout of the same data. Expansion In and Expansion Out pins implement an expansion scheme that allows individual FIFOs to be cascaded to greater depth without incurring additional latency (bubblethrough) delays. - LH5496 only. CMOS 512 × 9 FIFO PIN CONNECTIONS 28-PIN PDIP W D8 D3 D2 D1 D0 XI FF Q0 Q1 Q2 Q3 Q8 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC D4 D5 D6 D7 FL/RT RS EF XO/HF Q7 Q6 Q5 Q4 R 5496-1D TOP VIEW Figure 1. Pin Connections for PDIP...