HYM322030S module equivalent, 2m x 32-bit dynamic ram module.
RAS initialization cycles instead of 8 RAS cycles are required. 5) VIH (max) and VIL (max) are reference levels for measuring timing of input signals. Transition times ar.
DRAM Module (access time 60 ns) DRAM Module (access time 70 ns) DRAM Module (access time 60 ns) DRAM Module (access time 70 ns)
Semiconductor Group
561
09.94
HYM 322030S/GS-60/-70 2M × 32-Bit
The HYM 322030S/GS-60/-70 is a 8 M Byte DRAM module o.
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