time is controlled by tAA. 11)Either tRCH or tRRH must be satisfied for a read cycle. 12)tOFF (max.) define the time at which the outputs achieve the open-circuit condit.

Fast access and cycle time 60 ns access time 110 ns cycle time (-60 version) Fast page mode capability 40 ns cycle time .

DRAM Module (access time 60 ns) DRAM Module (access time 60 ns) Semiconductor Group 2 HYM 364020S/GS-60 4M × 36-Bit Pin Configuration Pin Names VSS DQ18 DQ19 DQ20 DQ21 N.C. A1 A3 A5 A10 DQ22 DQ23 DQ24 DQ25 N.C. A8 N.C. DQ26 1 DQ0 2 3 DQ1 4 5 DQ2.

HYM364020S

HYM364025GS-50

HYM364025GS-60

HYM364025S

HYM364035GS-60

HYM364035S

HYM361120

HYM361120GS-60

HYM361120GS-70

HYM361120S-60

HYM361120S-70

HYM361140GS-60

HYM361140GS-70