PEB2045
Key Features
- PCM-Input Ports: Serial data is received at these lines at standard TTL levels
- Address 0: When high, the indirect register access mechanism is enabled
- If A0 is logical 0 the mode and status registers can be written to and read respectively
- Chip Select: A low level selects the PEx 2045 for a register access operation
- Supply voltage: 5 V ± 5 %
- Read: This signal indicates a read operation and is internally sampled only if CS is active
- The MTSC puts data from the selected internal register on the data bus with the falling edge of RD
- 21 19 A0 I 22 23 24 20 21 22 CS I I I VDD RD Semiconductor Group 3 PEB 2045 PEF 2045 Pin Definitions and Functions (cont’d) Pin No
- P-DIP 23 Symbol WR Input (I) Function Output (O) I Write: This signal initiates a write operation
- The WR input is internally sampled only if CS is active
