SIS5501 Description
The chipset is developed by using a very high level of function integration and system partitioning. With the SiS5501, SiS5502, and SiS5503 chipset, only 12 TTLs (include 3 DRAM address buffer) are required to implement a low cost, high performance, Pentium/P54C PCI/ISA system. Figure 1 shows the system block diagram.
SIS5501 Key Features
- Supports the 51060, 56766, 73590, 815100 MHz and 75 MHz Pentium Processor Supports M1 and Other Pentium patible CPU Supp
- Write Through and Write Back Cache Modes
- 8 bits or 7 bits Tag with Direct Mapped Organization
- Supports Standard and Burst SRAMs
- Supports 64 KBytes to 2 MBytes Cache Sizes
- Cache Read/Write Cycle of 3-1-1-1 Using Burst SRAMs at 66 MHz
- Integrated DRAM Controller
- Supports 8 Banks of SIMMs up to 512 MBytes of Cacheable Main Memory
- Supports " Table- Free " DRAM Configuration
- Concurrent Write Back