SIS5501 Datasheet | Silicon Integrated System

Overview Si S5501 Si S5502 Si S5503 PCI/ISA Cache Memory Controller (PCMC) PCI Local Data Buffer (PLDB) PCI System I/O (PSIO) A whole set of the Si S5501, 5502, and 5503 provides fully integrated support for the Pentium/P54C PCI/ISA system. The chipset is developed by using a very high level of function integration and system partitioning. With the Si S5501, Si S5502, and Si S5503 chipset, only 12 TTLs (include 3 DRAM address buffer) are required to implement a low cost, high performance, Pentium/P54C PCI/ISA system. Figure 1 shows the system block diagram. SRAM Pentium , P54C 373 Address Data HOST BUS PCMC 5501 Address/Data DRAM PLDB 5502 PCI BUS PSIO IDE Buffers IDE Drives PCI Local Device #1 ISA Device #1 PCI Local Device #2 ISA Device #2 - - - - - - XD BUS 245 Address Data ISA BUS Figure 1.1 System Block Diagram Preliminary V2.0 April 2, 1995 Silicon Integrated Systems Corporation .. Si S5501 PCI/ISA Cache Memory Controller 2. Si S5501 2.1 Features - - - - Supports the 51060, 56766, 73590, 815100 MHz and 75 MHz Pentium Processor Supports M1 and Other Pentium patible CPU Supports the Pipelined Address Mode of the Pentium or the P54C Processor Integrated Second Level ( L2 ) Cache Controller - Write Through and Write Back Cache Modes - 8 bits or 7 bits Tag with Direct Mapped Organization - Supports Standard and Burst SRAMs - Supports 64 KBytes to 2 MBytes Cache...