SIS5501
Key Features
- Write Through and Write Back Cache Modes
- 8 bits or 7 bits Tag with Direct Mapped Organization
- Supports Standard and Burst SRAMs
- Supports 64 KBytes to 2 MBytes Cache Sizes
- Cache Read/Write Cycle of 3-1-1-1 Using Burst SRAMs at 66 MHz
- Integrated DRAM Controller
- Supports 8 Banks of SIMMs up to 512 MBytes of Cacheable Main Memory
- Supports " Table- Free " DRAM Configuration
- Concurrent Write Back
- CAS#-before-RAS# Transparent DRAM Refresh
