SiS85C471 Datasheet | Silicon Integrated Systems

85C471 Green PC ISA-VESA Single Chip 1. 85C471 OVERVIEW 1.1 Introduction The Si S85C471 single chip controller supports Intel's 80486DX2/DX/SX/SL Enhanced, P24D/P24T/P24C CPU, Cyrix's Cx486S2 (M6/M7) CPU and AMD's Am486DXL/DXL2 CPU. The Si S85C471 is a high performance, 100% PC/AT patible single chip controller, designed for cached/non-cached P24D/P24T/P24C, M6/M7 or 486 PC systems. The high integration of the powerful cache controller, the DRAM controller, the CPU interfaces, the bus controller, the data buffers and the peripheral controllers provides an easy and economical solution for pact board manufacturing. In addition to supporting burst reads for the cache line fills of the CPU, the Si S85C471 is capable of accepting burst write data of the CPU's internal cache dirty line(s) during CPU write-back cycles. The support of the CPU burst write cycle is optional through the control of the Configuration Registers. The Si S85C471 supports the cache size up to 1 MB and the DRAM size up to 128 MB. The Si S85C471 has a built-in cache controller which supports direct mapped writethrough/write-back cache. The programmable AT-bus clock supports are patible with AT-bus timing requirements for different PC systems. In addition, the local bus interfaces, the integration of the DMA Controllers, Interrupt Controllers and Timers/Counters are designed to be a higher performance, more pact, and more cost-effective product for a P24D/P24T/P24C, 486SX/DX/DX2/SL-Enhanced, Am486DXL/DXL2, or a Cx486S2 (M6/M7) PC/AT system. The Si S85C471 provides power saving Features to allow a system, through the control of BIOS, to reduce the CPU clock frequency from 50MHz down to 0 MHz(STOP CLOCK) when the system is idle. To support the SL-Enchanced 486, M6/M7, P24D/P24T/P24C's Am486DXL/DXL2 STPCLK/SMI Features , the Si S85C471 also implements the corresponding logics to support STPCLK /SMI for power saving. The Si S85C471 supports the VL-Bus applications including (1) CPU accesses VL-Bus...