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Si5355
A N Y - F REQUENCY 1–200 MH Z Q UAD F REQUENCY 8-O UTPUT C LOCK G ENERATOR
Features
Generates any frequency from 1 to 200 MHz on each of the 4 output banks Eight CMOS clock outputs Guaranteed 0 ppm frequency synthesis error for any combination of frequencies 25 or 27 MHz xtal or 5–200 MHz input clk Five programmable control pins (output enable, frequency select, reset) Separate OEB pins to disable individual banks or all outputs Loss of signal output Low 50 ps (typ) pk-pk period jitter Phase jitter: 2 ps rms 12 kHz–20 MHz
Excellent PSRR performance eliminates need for external power supply filtering Low power: 45 mA (core) Core VDD: 1.8, 2.5, or 3.3 V Separate VDDO for each bank of outputs: 1.8, 2.5, or 3.