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39VF010 Datasheet Preview

39VF010 Datasheet

SST39VF010

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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
SST39LF/VF512 / 010 / 020 / 0403.0 & 2.7V 512Kb / 1Mb / 2Mb / 4Mb (x8) MPF memories
FEATURES:
Data Sheet
• Organized as 64K x8 / 128K x8/ 256K x8 / 512K x8
• Single Voltage Read and Write Operations
– 3.0-3.6V for SST39LF512/010/020/040
– 2.7-3.6V for SST39VF512/010/020/040
• Superior Reliability
Endurance: 100,000 Cycles (typical)
Greater than 100 years Data Retention
• Low Power Consumption:
Active Current: 10 mA (typical)
Standby Current: 1 µA (typical)
• Sector-Erase Capability
Uniform 4 KByte sectors
• Fast Read Access Time:
45 ns for SST39LF512/010/020/040
55 ns for SST39LF020/040
70 and 90 ns for SST39VF512/010/020/040
• Latched Address and Data
• Fast Erase and Byte-Program:
Sector-Erase Time: 18 ms (typical)
Chip-Erase Time: 70 ms (typical)
Byte-Program Time: 14 µs (typical)
Chip Rewrite Time:
1 second (typical) for SST39LF/VF512
2 seconds (typical) for SST39LF/VF010
4 seconds (typical) for SST39LF/VF020
8 seconds (typical) for SST39LF/VF040
• Automatic Write Timing
Internal VPP Generation
• End-of-Write Detection
Toggle Bit
Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard
Flash EEPROM Pinouts and command sets
• Packages Available
32-lead PLCC
32-lead TSOP (8mm x 14mm)
48-ball TFBGA (6mm x 8mm) for 1 Mbit
PRODUCT DESCRIPTION
The SS T39LF512/010/020/040 an d S ST39VF512/010/
020/040 are 64K x8 , 128K x8, 256K x 8 an d 5124K x 8
CMOS Multi-Purpose F lash (MPF) manuf actured wit h
SSTs pr oprietary, hi gh p erformance CM OS S uperFlash
technology. The split-gate cell design and thick oxide tun-
neling injector attain better reliability and manufacturability
compared with alternate approaches. The SST39LF512/
010/020/040 devices write (Program or Erase) with a 3.0-
3.6V pow er su pply. The SS T39VF512/010/020/040
devices write with a 2.7-3.6V power supply. The devices
conform to JEDEC standard pinouts for x8 memories.
Featuring hi gh performance B yte-Program, th e
SST39LF512/010/020/040 a nd SST39VF512/010/020/
040 devices provide a maximum Byte-Program time of 20
µsec. These devices use Toggle Bit or Data# Polling to indi-
cate the co mpletion of Pr ogram op eration. T o pr otect
against inadvertent write, they have on-chip hardware and
Software Data P rotection s chemes. Designed, manufac-
tured, and tested for a wide spectrum of applications, they
are offered with a guaranteed endurance of 10,000 cycles.
Data retention is rated at greater than 100 years.
The SS T39LF512/010/020/040 an d S ST39VF512/010/
020/040 d evices ar e s uited f or ap plications th at r equire
convenient and economical updating of program, configu-
ration, or data memory. For all s ystem a pplications, they
significantly improves performance and reliability, while low-
ering power consumption. They inherently use less energy
during Erase and Program than alternative flash technolo-
gies. T he to tal en ergy c onsumed i s a f unction of th e
applied voltage, current, and time of application. Since for
any given voltage range, the SuperFlash technology uses
less current to program and has a shorter erase time, the
total energy consumed during any Erase or Program oper-
ation i s less than alternative fl ash te chnologies. T hese
devices also improve flexibility while lowering the cost for
program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
To m eet s urface m ount r equirements, t he SST39LF512/
010/020/040 a nd SST39VF512/010/020/040 d evices a re
offered in 32-lead PLCC and 32-lead TSOP packages. The
39LF/VF010 is also offered in a 48-ball TFBGA package.
See Figures 1 and 2 for pinouts.
©2001 Silicon Storage Technology, Inc.
S71150-03-000 6/01
395
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
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Silicon Storage Technology

39VF010 Datasheet Preview

39VF010 Datasheet

SST39VF010

No Preview Available !

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the SST39LF512/010/020/040 and
SST39VF512/010/020/040 device i s controlled b y C E#
and OE#, both have to be low for the system to obtain data
from the outputs. CE# is used for device selection. When
CE# is high, the chip is deselected and only standby power
is consumed. OE# is the output control and is used to gate
data from the output pins. The data bus is in high imped-
ance state when either CE# or OE# is high. Refer to the
Read cycle timing diagram for further details (Figure 4).
Byte-Program Operation
The SS T39LF512/010/020/040 an d S ST39VF512/010/
020/040 are programmed on a byte-by-byte basis. Before
programming, one must ensure that the sector, in which
the byte which is being programmed exists, is fully erased.
The Program operation consists o f three steps. The first
step is the thr ee-byte-load s equence f or So ftware Dat a
Protection. The second step is to load byte address and
byte dat a. Du ring th e By te-Program ope ration, th e
addresses are latched on the falling edge of either CE# or
WE#, whichever occurs last. The data is latched on the ris-
ing edge of either CE# or WE#, whichever occurs first. The
third step is the internal Program operation which is initi-
ated after the rising edge of the fourth WE# or CE#, which-
ever occurs first. The Program operation, once initiated, will
be completed, within 20 µs. See Figures 5 and 6 for WE#
and CE # c ontrolled Pr ogram op eration ti ming diagrams
and Figure 15 for flowcharts. During the Program opera-
tion, the only valid reads are Data# Polling and Toggle Bit.
During the internal Program operation, the host is free to
perform additional tasks. Any commands written during the
internal Program operation will be ignored.
Sector-Erase Operation
The Sector-Erase operation alows the system to erase the
device on a sector-by-sector basis. The sector architecture
is based on uniform sector size of 4 KByte. The Sector-
Erase operation is i nitiated b y executing a s ix-byte-com-
mand sequence with Sector-Erase c ommand (30H) and
sector a ddress (S A) i n t he l ast b us c ycle. Th e s ector
address is l atched on the falling edge of t he sixth WE#
pulse, while the command (30H) is latched on the rising
edge of the sixth WE# pulse. The internal Erase operation
begins after the sixth WE# pulse. The End-of-Erase can be
determined using either Data# Polling or Toggle Bit meth-
ods. See Figure 9 for timing waveforms. Any commands
written during the Sector-Erase operation will be ignored.
Chip-Erase Operation
The SS T39LF512/010/020/040 an d S ST39VF512/010/
020/040 d evices pr ovide a Chip-Erase o peration, which
allows the user to erase the entire memory array to the1s
state. This is useful when the entire device must be quickly
erased.
The Chip-Erase operation is initiated by executing a six-
byte S oftware Data Protection command se quence with
Chip-Erase command (10H) with address 5555H in thelast
byte sequence. The internal Erase operation begins with
the rising edge of the sixth WE# or CE#, whichever occurs
first. During the internal Erase operation, the only valid read
is Toggle Bit or Data# Polling. See Table 4 for the command
sequence, Figure 10 for timing diagram, and Figure 18 for
the flowchart. An y c ommands wr itten dur ing the Chi p-
Erase operation wil be ignored.
Write Operation Status Detection
The SS T39LF512/010/020/040 an d S ST39VF512/010/
020/040 devices provide two software means to detect the
completion of a Write (Program or Erase) cycle, in order to
optimize the system write cycle time. The software detec-
tion includes two status bits: Data# Polling (DQ7) and Tog-
gle Bit (DQ6). The End-of-Write detection mode is enabled
after the rising edge of WE# which initiates the internal Pro-
gram or Erase operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should in clude a loop to r ead th e accessed l ocation a n
additional two (2) times. If bo th reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion isvalid.
©2001 Silicon Storage Technology, Inc.
2
S71150-03-000 6/01 395


Part Number 39VF010
Description SST39VF010
Maker Silicon Storage Technology
Total Page 24 Pages
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