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CD4030B Datasheet Preview

CD4030B Datasheet

CMOS Quad 2-Input Exclusive-OR gate

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   CMOS High Voltage Logic  CD4030B
 
CMOS Q uad 2-Input Exclusive-OR gate in bare die form
Rev 1.0
19/09/18
Descrip  tion
Features:
The CD403 0B provides the system designer with direct
implementation of the Exclusive-OR function. The
danedvicceonhfaosrm esqutoalsstaonudrcaerdaBndsseirniekscouurrtepnutt
capabilities
drive.
Dcheavriacecteoruistp tiuctssbayreprbouvfifdeirnegdvwehryichhigimhpgraoivne. sTtrhaendsfeevrice
is capable of driving x2 low power TTL loads or x1
LSTTL load  . The CD4030B is primarily used for higher
voltage acceptance and where low power dissipation
and/or high  noise immunity are required.
 
ƒ High Input Voltage up to 20V
ƒ Symmetrical Output Characteristics
ƒ Max input current 1µA at 18V over full Military
Temperature Range
ƒ Low Power TTL compatible
ƒ Specified at 5V, 10V & 15V
ƒ Direct drop-in replacement for obsolete
components in long term programs.  
Orderin  g Information
 
The following part suffixes apply:
ƒ No suff ix - MIL-STD-883 /2010B Visual Inspection
ƒ H” - M IL-STD-883 /2010B Visual Inspection
+ MIL- PRF-38534 Class H LAT
ƒ K” - MIL-STD-883 /2010A Visual Inspection (Space)
+ MIL- PRF-38534 Class K LAT
LAT = Lot  Acceptance Test.
For further information on LAT process flows see below.
www.silico nsupplies.com\quality\bare-die-lot-qualification
Die Dimensions in µm (mils)
1524 (60)
Supply  Formats:
 
ƒ Default – Die in Waffle Pack (400 per tray capacity)
ƒ Sawn W  afer on Tape – On request
ƒ Unsaw n Wafer – On request
ƒ Die Thi ckness <> 635µm(25 Mils) – On request
ƒ Assem bled into Ceramic Package – On request
Mechanical Specification
Die Size (Unsawn)
Minimum Bond Pad Size
Die Thickness
Top Metal Composition
Back Metal Composition
1524 x 1270
50 x 37
µm
mils
102 x 102
4x4
µm
mils
635 (±20)
25 (±0.79)
µm
mils
Al 1%Si 1.1µm
N/A – Bare Si
Page 1 of 5 
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Silicon Supplies

CD4030B Datasheet Preview

CD4030B Datasheet

CMOS Quad 2-Input Exclusive-OR gate

No Preview Available !

  CMOS High Voltage Logic  CD4030B
d 
Pad La  yout and Functions
 
 1
2
 
14 13
DIE ID
 3
 
4
 
5
 
6
 
7
8
  1524µm (60 mils)
 
 
 
Logic  Diagram
 
 
 
 
 
 
12
11
10
9
Rev 1.0
19/09/18
PAD
FUNCTION
1 1A
2 1B
3 1Y
4 2Y
5 2A
6 2B
7 VSS
8 3A
9 3B
10 3Y
11 4Y
12 4A
13 4B
14 VDD
CONNECT CHIP BACK TO VDD OR FLOAT
Truth Table
INPUTS
AB
OUTPUT
Y
LL
HL
LH
HH
L
H
H
L
H = High level (steady state)
L = Low level (steady state)
  Y=AB
 
  Pad 14 = VDD
Pad 7 = VSS
 
Page 2 of 5 
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Part Number CD4030B
Description CMOS Quad 2-Input Exclusive-OR gate
Maker Silicon Supplies
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CD4030B Datasheet PDF






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