Full PDF Text Transcription for 2N5018 (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
2N5018. For precise diagrams, and layout, please refer to the original PDF.
0- -oan p-channel JFETs Z C"'4 designed for • • • co - •oan Analog Switches Z •C"'4 Commutators • Choppers ~-~~--- H Siliconix Performance Curves PSA/PSB See Section 4 BE...
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oppers ~-~~--- H Siliconix Performance Curves PSA/PSB See Section 4 BENEFITS • Low Insertion Loss rOS(on) < 75 n (2N5018) • No Offset or Error Voltages Generated by Closed Switch Purely Resistive *ABSOLUTE MAXIMUM RATINGS (25°C) Reverse Gate-Drain or Gate-Source Voltage (Note 1) Gate Current Total Device Dissipation, Free-Air (Derate 3 mW;oC) Storage Temperature Range Lead Temperature (1/16" from case for 60 seconds) 30V .50mA 500mW -65 to +200°C 300°C TO-1B See Section 6 .
2N5018 Datasheet
