LIST OF CONTENT
ST75256
1 INTRODUCTION ...................................................................................... 1
2 FEATURES .............................................................................................. 1
3 PAD ARRANGEMENT............................................................................. 2
4 PAD CENTER COORDINATES ............................................................... 3
5 BLOCK DIAGRAM................................................................................. 11
6 PIN DESCRIPTION ................................................................................ 12
6.1 POWER SUPPLY PINS ...............................................................................................12
6.2 DRIVER OUTPUT PINS...............................................................................................14
6.3 CLOCK SYSTEM INPUT ..............................................................................................15
6.4 INTERFACE LOGIC PINS.............................................................................................16
6.5 MASTER/SLAVE PINS................................................................................................18
6.6 OTP PINS................................................................................................................19
6.7 TEST PINS ...............................................................................................................19
6.8 ITO RESISTANCE LIMITATION ....................................................................................19
6.9 ITO LAYOUT GUIDE ..................................................................................................20
6.10 ITO LAYOUT REFERENCE.......................................................................................21
6.11 FOR VPP .............................................................................................................23
6.12 ENHANCE ESD PERFORMANCE FOR COG APPLICATION ...........................................23
7 FUNCTION DESCRIPTION.................................................................... 24
7.1 MICROPROCESSOR INTERFACE..................................................................................24
7.1.1 Chip Select Input ....................................................................................................................................... 24
7.1.2 Parallel / Serial Interface ........................................................................................................................... 24
7.1.3 Parallel Interface ....................................................................................................................................... 24
7.1.4 Setting Serial Interface .............................................................................................................................. 25
7.1.5 4-Line Serial Interface ............................................................................................................................... 25
7.1.6
7.1.7
3-Line Serial Interface ............................................................................................................................... 26
I2C Interface .............................................................................................................................................. 27
7.2 DATA TRANSFER ......................................................................................................31
7.3 DISPLAY DATA RAM (DDRAM) ................................................................................32
7.3.1 Page Address Circuit................................................................................................................................. 34
7.3.2 Column Address Circuit............................................................................................................................. 34
7.3.3 I/O Buffer Circuit........................................................................................................................................ 34
7.3.4 Display Data Latch Circuit ......................................................................................................................... 34
Version 1.6b
2015/6
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