Datasheet4U Logo Datasheet4U.com

AA116-72LF - 4 MHz-2 GHz 1-Bit Digital Attenuator

Description

The AA116-72LF is a one-bit GaAs FET digital attenuator in a lowcost SOT-5 package.

The device has a Least Significant Bit (LSB) of 15 dB and is particularly suited where high attenuation accuracy, low insertion loss, and low intermodulation products are required.

Features

  • 3 V control.
  • Low loss.
  • Small SOT-5 package (MSL1, 260 C per JEDEC J-STD-020) Skyworks offers lead (Pb)-free RoHS (Restriction of Hazardous Substances) compliant packaging. J1 15 dB J2 S2182 Figure 1. AA116-72LF Block Diagram.

📥 Download Datasheet

Datasheet Details

Part number AA116-72LF
Manufacturer Skyworks Solutions
File Size 243.93 KB
Description 4 MHz-2 GHz 1-Bit Digital Attenuator
Datasheet download datasheet AA116-72LF Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
AA116 SCRs .5 A/ Planar Microsemi Corporation
AA110 SCRs .5 A/ Planar Microsemi Corporation
AA110-85 GaAs IC 5 Bit Digital Attenuator with Driver 1 dB LSB Positive Control DC-2 GHz Alpha Industries
AA1102W LED STANLEY ELECTRIC
AA111 SCRs .5 A/ Planar Microsemi Corporation

Other Datasheets by Skyworks Solutions

Part Number Description
AA116-72 GaAs IC 1-Bit Digital Attenuator

Full PDF Text Transcription

Click to expand full text
DATA SHEET AA116-72LF: 4 MHz-2 GHz 1-Bit Digital Attenuator (15 dB LSB) Applications  Cellular radio  Wireless data systems  WLL gain level control circuits Features  3 V control  Low loss  Small SOT-5 package (MSL1, 260 C per JEDEC J-STD-020) Skyworks offers lead (Pb)-free RoHS (Restriction of Hazardous Substances) compliant packaging. J1 15 dB J2 S2182 Figure 1. AA116-72LF Block Diagram Description The AA116-72LF is a one-bit GaAs FET digital attenuator in a lowcost SOT-5 package. The device has a Least Significant Bit (LSB) of 15 dB and is particularly suited where high attenuation accuracy, low insertion loss, and low intermodulation products are required. A functional block diagram is shown in Figure 1. The pin configuration and package are shown in Figure 2.
Published: |