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Supertex

TN05C Datasheet Preview

TN05C Datasheet

N-Channel Enhancement-Mode Vertical DMOS Power FETs

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(1) §upertexinc.
TN05C
N-Channel Enhancement-Mode
Vertical DMOS Power FETs
Ordering Information
BVDSS '
BVDGS
200V
240V
RDS(ON)
(max)
100
100
ID(ON)
(min)
300mA
300mA
VGS(th)
(max)
1.5V
1.5V
TO·39
TN0520N2
TN0524N2
Order Number' Package
T0-92
DICE
TN0520N3
TN0520ND
TN0524N3
TN0524ND
Features
0 Freedom from secondary breakdown
0 Low power drive requirement
0 Ease of paralleling.
0 Low CISS and fast switching speeds
0 Excellent thermal stability
0 Integral Source-Drain diode
0 High input impedance and high gain
0 Very low threshold voltage
Applications
o Telecommunications: Outpulsing switch
Muting switch
o Battery operated systems
o Solid state relays
Advanced DMOS Technology
These enhancement-mode (normally-off) power transistors util-
ize a vertical DMOS structure and Supertex's well-proven silicon-
gate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar tram:i.stors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermally-
induced secondary breakdown.
Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high break-
down voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.
Package Options
(Notes 1 and 2)
Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature"
*Oistance of 1.6 mm from case for 10 seconds.
±20V
-55°C to +150°C
300°C
7-10
TO-39
TO-92
Note t: See Package Outline section for discrete pinouts.
Note 2: See Array section for quad pinouts.




Supertex

TN05C Datasheet Preview

TN05C Datasheet

N-Channel Enhancement-Mode Vertical DMOS Power FETs

No Preview Available !

Thermal Characteristics
Package
ID (continuous)"
ID (pulsed)"
TO-39
TO-92
0.7A
0.3A
* ID (continuous) is limited by max rated Tr
1.5A
1.0A
Power Dissipation
@Tc=25°C
3.5W
1.0W
eje
°C/W
35
125
ej •
°CIW
125
170
IDR
0.7A
0.3A
TN05C
IDRM"
1.5A
1.0A
Electrical Characteristics (@ 25°C unless otherwise specified)
(Notes 1 and 2)
Symbol
BVoss
VGS(thl
I1VGSlth)
IGSS
loss
Parameter
Min Typ Max Unit
Drain-to-Source
Breakdown Voltage
I TN0524
I TN0520
240
200
V
Gate Threshold Voltage
0.6 1.5 V
Change in VGSlth) with Temperature
Gate Body Leakage
-3.0 -4.0 mV/oC
100 nA
Zero Gate Voltage Drain Current
10
r---soo- ~A
101ON)
ON-State Drain Current
100 390
300 800
mA
ROSION)
Static Drain-to-Source
ON-State Resistance
9 15 0
7 10
I1ROSION)
GFS
CISS
Coss
CRSS
tdloNI
tr
tdOFF
tf
Vso
trr
Change in ROSION) with Temperature
Forward Transconductance
Input Capacitance
Common Source Output Capacitance
Reverse Transfer Capacitance
Turn-ON Delay Time
Rise Time
Turn-OFF Delay Time
Fall Time
Diode Forward Voltage Drop
Reverse Recovery Time
0.9
0.15 0.3
45
15
3
3
3
5
3
1.1
400
1.5 %/oC
U
60
35 pF
8
5
5
ns
7
5
2.5 V
ns
Note 1: All D.C. parameters 100% tested at 25°C unlass otherwise stated. (Pulse test: 300~s pulse, 2% duty cycle.)
Note 2: All A.C. parameters sample tested.
Conditions
VGs=0,10 =1mA
VGS = Vos' 10 = 1.0mA
VGS = Vos' 10 = 1.0mA
VGS = ±20V, Vos = 0
VGS = 0, Vos = Max Rating
Vos = 0, VGS = 0.8 Max Rating
TA = 125°C
VGS = 3V, Vos = 25V
VGS = 5V, Vos= 25V
VGS = 3V, 10 = 50mA
VGS = 5V, 10 = 100mA
VGS = 5V, 10 = 0.2A
Ves = 25V,!o = 0.2A
VGS = 0, Vos = 25V
f= 1 MHz
Voo =25V
10 = 0.2A
Rs =500
VGS = 0, Iso = 100mA
VGS = 0, Iso = 100mA
-
Switching Waveforms and Test Circuit
t(ON)
td(ON) tr
Output _ _ _ _~
10%
t(OFF)
II----PU~E---I
GENERATOR
1
1--',"",-1:) SCOPE
1
\~~+-~~-+~
D.U.T.
1
1
1
1
1
I'"
1
'----- ______1
7-11


Part Number TN05C
Description N-Channel Enhancement-Mode Vertical DMOS Power FETs
Maker Supertex
Total Page 4 Pages
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