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TN0606N6 Datasheet

N-Channel Enhancement-Mode Vertical DMOS Power FETs Quad Array

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" §upertexinc.
TN0606N6
TN0606N7
I
N-Channel Enhancement-Mode
Vertical DMOS Power FETs Quad Array
Ordering Information
BVoss '
BVDGS
60V
*14-pin Side Brazed Ceramic Dip.
ROS(ON)
(max)
1.50
Order Number' Package
14-Pin P-Dip
I 14-Pin C-Dip·
TN0606N6
I TN0606N7
Features
D 4 independent channels
D 4 electrically isolated die
D Commercial and Military versions available
D Freedom from secondary breakdown
D Low power drive requirement
D Low C,ss and fast switching speeds
D High input impedance and high gain
Applications
D Motor control
D Convertors
D Amplifiers
D Switches
D Power supply circuits
D Driver (Relays, Hammers, Solenoids, Lamps,
Memories. Displays, Bipolar Transistors. etc.)
Advanced DMOS Technology
These enhancement-mode (normally-off) power transistors util-
ize a vertical DMOS structure and Supertex's well-proven silicon-
gate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermally-
induced secondary breakdown.
Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high break-
down voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.
Electrical Characteristics
Refer to TN06A Data Sheet for detailed characteristics.
Pin Configuration
Thermal Characteristics
Package
Plastic
DIP
10 continuous & IDA (single die)
1.4A
Ceramic
DIP
1.60A
10 pulsed- & lOAM'
Power Dissipation @ Tc = 25°C*
0ja (OCIW)
0je (OCIW)
+ Pulse test 300 I1S pulse. 2% duty cycle.
t Total for package.
6.0A
3W
83.3
41.6
6.0A
4W
62.5
31.2
top view
14-pin DIP
10-19


Part Number TN0606N6
Description N-Channel Enhancement-Mode Vertical DMOS Power FETs Quad Array
Maker Supertex
Total Page 1 Pages
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