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Supertex

VP05D Datasheet Preview

VP05D Datasheet

P-Channel Enhancement-Mode Vertical DMOS FETs

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o !iupertex inc.
VP05D
Ordering Information
BVoss '
BVOGS
-350V
-400V
ROS(ON)
(max)
750
750
P-Channel Enhancement-Mode
Vertical DMOS Power FETs
IO(ON)
(min)
-200m A
-200mA
TO·39
Order Number' Package
TO·92
VP0535N2
VP0535N3
VP0540N2
VP0540N3
DICE
VP0535ND
VP0540ND
Features
o Freedom from secondary breakdown
o Low power drive requirement
o Ease of paralleling
o Low CISS and fast switching speeds
o Excellent thermal stability
o Integral Source-Drain diode
o High input impedance and high gain
o Complementary N- and P-Channel devices
Advanced DMOS Technology
These enhancement-mode (normally-off) power transistors util-
ize a vertical DMOS structure and Supertex's well-proven silicon-
gate manufacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inherent in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermally-
induced secondary breakdown.
Supertex Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high break-
down voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.
Applications
Package Options
(Notes 1 and 2)
0 Motor control
0 Convertors
0 Amplifiers
0 Switches
o Power supply circuits
o Driver (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)
i
Absolute Maximum Ratings
TO-92
TO·39
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature"
*Oistance of 1.6 mm from case for 10 seconds.
±20V
-55°C to +150°C
300°C
Note 1: See Package Outline section for discrete pinouts.
Note 2: See Array section for quad pinouts.
9-31




Supertex

VP05D Datasheet Preview

VP05D Datasheet

P-Channel Enhancement-Mode Vertical DMOS FETs

No Preview Available !

Thermal Characteristics
VPOSD
.
Package
10 (continuous)"
10 (pulsed)"
Power Dissipation
~c
811
lOR 10RM
@Tc=25°C
°CIW
°CIW
TO· 39
TO· 92
-0.2A
-O.lA
,. 10 (continuous) IS limited by max rated Tj.
-O.SA
-0.5A
3.5W
1.0W
35 125
125 170
Electrical Characteristics (@ 25°C unless otherwise specified)
-0.2A
-O.lA
-0.5A
-0.5A
(Notes 1 and 2)
Symbol
BVDSS
Parameter
Min Typ Max Unit
Conditions
Drain·to·Source
Breakdown Voltage
VP0540
VP0535
-400
-350
V VGS = 0,10 =-lmA
VGS(th)
LWGS(th)
IGSS
IDSS
Gate Threshold Voltage
Change in VGS(th) with Temperature
Gate Body Leakage
Zero Gate Voltage Drain Current
-2.5
-3.5
-4.5
-6.0
-100
-10
t---
-500
V
mV/'C
nA
/LA
ID(ON)
RDS(ON)
lIRDS(ON)
GFS
CISS
COSS
CRSS
td(ON)
tr
td(OFF)
tf
VSD
trr
ON·State Drain Current
Static Drain·to·Source
ON·State Resistance
Change in RDS(ON) with Temperature
Forward Transconductance
Input Capacitance
Common Source Output Capacitance
Reverse Transfer Capacitance
Turn·ON Delay Time
Rise Time
Turn·OFF Delay Time
Fall Time
Diode Forward Voltage Drop
Reverse Recovery Time
200
50
-80
-250
60
45
0.8
70
40
11
3
-0,8
200
75
1.5
60
20
5
10
15
15
10
-1.5
mA
\'l
%/'C
mU
pF
ns
V
ns
Note 1: All D.C. parameters 100% tested at 25'C unless otherwise stated. (Pulse test: 300~s pulse, 2% duty cycle.)
Note 2: All A.C. parameters sample tested.
VGS= VDS,ID=-lmA
VGS = VDS, ID = -lmA
VGS - ±20V, VDS - 0
VGS - 0, VDS - Max Rating
VGS = 0, VDS = 0.8 Max Rating
TA = 125'C
VGS =-5V, VDS =-25V
VGS=-10V, VDS=-25V
VGS =-5V, ID =-10mA
VGS =-10V, ID =-50mA
VGS=-10V,ID=-50mA
VDS = -25V, ID =-50mA
VGS = 0, VDS =-25V
f= 1 MHz
VDD =-25V
ID=-50mA
RS= 50.11
VGS=O,ISD=-O.lA
VGS = 0, ISD =-0.1 A
Switching Waveforms and Test Circuit
INPUT
OUTPUT
r-;;:;L-;--'
I GENERATOR
I
I--'~-OSCOPE
I \~I~+---~
D.U.T.
II
:I
IL _____ JI
9·32


Part Number VP05D
Description P-Channel Enhancement-Mode Vertical DMOS FETs
Maker Supertex
Total Page 4 Pages
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