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Supertex

VP06D Datasheet Preview

VP06D Datasheet

P-Channel Enhancement-Mode Vertical DMOS FETs

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"§upertexinc.
VP06D
P-Channel Enhancement-Mode
Vertical DMOSPower FETs
Ordering Information
BVoss /
BVOGS
-350V
-400V
ROS(ON)
(max)
250
250
IO(ON)
(min)
-O.4A
-O.4A
TO·3f
VP0635N2
VP0640N2
Orur Number / Package
T0.92
TO·220
VP0635N3
VP0635N5
VP0640N3
VP0640N5
DICE
VP0635ND
VP0640ND
Features
o Freedom from secondary breakdown
o Low power drive requirement
o Ease of paralleling
o Low CISS and fast switching speeds
o Excellent thermal stability
o Integral Source-Drain diode
o High input impedance and high gain
o Complementary N- and P-Channel devices
Advanced DMOS Technology
These enhancement-mode (normally-off) power transistors util-
ize a vertical DMOS structure and Supertex's well-proven silicon-
gate mar11.lfacturing process. This combination produces devices
with the power handling capabilities of bipolar transistors and with
the high input impedance and negative temperature coefficient
inhereflt in MOS devices. Characteristic of all MOS structures,
these devices are free from thermal runaway and thermally-
induced secondary breakdown.
Supertax Vertical DMOS Power FETs are ideally suited to a wide
range of switching and amplifying applications where high break-
down voltage, high input impedance, low input capacitance, and
fast switching speeds are desired.
Applications
o Motor control
o Convertors
o Amplifiers
o Switches
o Power supply circuits
o Driver (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)
Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature"
*Oistance of 1.6 mm from case for 10 seconds.
±20V
-55°C to +150°C
300°C
Package Options
(Notes 1 and 2)
if
TO·39
~
TO-220
i
TO-92
Note 1; See Package Outline section tor discrete pinouts.
9-39




Supertex

VP06D Datasheet Preview

VP06D Datasheet

P-Channel Enhancement-Mode Vertical DMOS FETs

No Preview Available !

Thermal Characteristics
Package
10 (continuous)"
10 (pulsed)"
TO-92
.. -0~30A
TO-39
-0.40A
TO-220
-0.40A
• 10 (continuous) is limited by max rated Tr
-O.SA
-0.75A
-0.75A
Power Dissipation
'@>Tc =25°C
lW
SW
28W
61e
°C/W
125
21
2.7
618
O(;/W
170
125
70
VPOSD
lOR 10RM"
-0.30A
-0.40A
-0.40A
:O.SA
-0.75A
-0.75A
Electrical Characteristics (@ 25°C unless otherwise specified)
(Notes 1 and 2)
Symbol
Parameter
Min Typ Max Unit
BVoss
Drain-to-Source
Breakdown Voltage
I VPOS40
I VPOS35
-400
-350
V
VGs(th)
Gate Threshold Voltage
-2 -4 V
tNGs(th)
Change in VGs(th) with Temperature
-4.8 mV/oC
IGss Gate Body Leakage
-100 nA
loss Zero Gate Voltage Drain Current
-10 itA
-1 mA
10(ON)
ON-State Drain Current
-300
-400 -550
mA
ROS(ON)
Static Drain-to-Source
ON-State Resistance
20
0
19 25
.1.R OS (ON)
GFS
Change in ROS ON) with Temperature
Forward Transconductance
100
0.75 o/oI°C
mU
C1ss
Coss
CRSs
Input Capacitance
Common Source Output Capacitance
Reverse Transfer Capacitance
75 130
50 75
10 20
pF
tdON
. tr
td(OFF)
~
Turn-ON Delay Time
Rise Time
Turn-OFF Delay Time
Fall Time
10
10
ns
20
10
Vso Diode Forward Voltage Drop
trr Reverse Recovery Time
1.8 V
300 ns
Note 1: All D.C. parameters 100% tested at 25'C unless otherwise stated. (Pulse test: 300l1s pulse. 2% duty cycle.)
Note 2: All A.C. parameters sample tested.
Conditions
VGS = 0, 10 = -2mA
VGS = Vos' 10 = -2mA
VGs = VDS' 10 = -2mA
VGs = ±20V, Vos = 0
VGS = 0, Vos = Max Rating
VGS = 0, Vos = 0.8 Max Rating
TA = 125°C
VGS = -5V, Vos = -25V
VGS = -10V, Vos = -25V
VGS = -5V, 10 = -100mA
VGS = -10V, 10 = -100mA
VGS = -10V, 10= -100mA
VDS = -25V, 10 = -100mA
VGS = 0, Vos = -25V
f= 1 MHz
Voo= -25V
10 = -100mA
Rs = 500
VGS = 0, Iso = -100mA
VGS = 0, Iso = -100mA
Switching Waveforms and Test Circuit
t(ON)
Output .,.-_ _ _~
10%
t(OFF)
1----puLSE---1
i GENERATOR
I
I---~-O SCOPE
I rv-+~+-~-+~
I
I
I
I
iI
7
I
~---- ______I
D.U.T.
9-40


Part Number VP06D
Description P-Channel Enhancement-Mode Vertical DMOS FETs
Maker Supertex
Total Page 4 Pages
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