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System Logic Semiconductor

4030B Datasheet Preview

4030B Datasheet

Quad Exclusive-OR Gate

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SL4030B
Quad Exclusive-OR Gate
High-Voltage Silicon-Gate CMOS
The SL4030B types consist of four independent Exclusive-OR
gates. The SL4030B provides the system designer with a means for
direct implementation of the Exlusive-OR function.
Operating Voltage Range: 3.0 to 18 V
Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
SL4030BN Plastic
SL4030BD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 14 =VCC
PIN 7 = GND
FUNCTION TABLE
Inputs
AB
LL
LH
HL
HH
Output
Y
L
H
H
L
SLS
System Logic
Semiconductor




System Logic Semiconductor

4030B Datasheet Preview

4030B Datasheet

Quad Exclusive-OR Gate

No Preview Available !

SL4030B
MAXIMUM RATINGS*
Symbol
Parameter
Value
VCC DC Supply Voltage (Referenced to GND)
VIN DC Input Voltage (Referenced to GND)
VOUT DC Output Voltage (Referenced to GND)
IIN DC Input Current, per Pin
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
PD Power Dissipation per Output Transistor
Tstg Storage Temperature
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
-0.5 to +20
-0.5 to VCC +0.5
-0.5 to VCC +0.5
±10
750
500
100
-65 to +150
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
Unit
V
V
V
mA
mW
mW
°C
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
VIN, VOUT
TA
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Min Max Unit
3.0 18
V
0 VCC
-55 +125
V
°C
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND(VIN or VOUT)VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
SLS
System Logic
Semiconductor


Part Number 4030B
Description Quad Exclusive-OR Gate
Maker System Logic Semiconductor
Total Page 4 Pages
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