Every effort has been made to ensure the accuracy of the information contain herein. If you find errors or
inconsistencies please bring them to our attention. In all cases, however, the Verilog HDL source code for
the Y8002 design defines “proper operation”.
Copyright © 2003, 2009, 2012, Systemyde International Corporation. All rights reserved.
“Z8000”, “Z8001”, “Z8002” and “Zilog” are registered trademarks of Zilog, Inc. All uses of these terms in
this document are to be construed as adjectives, whether or not the noun “microprocessor”, “CPU” or
“device” are actually present.