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Texas Instruments (TI) Electronic Components Datasheet

54AC11533 Datasheet

OCTAL D-TYPE TRANSPARENT LATCHES

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8-Latches in a Single Package
3-State Bus-Driving Inverting Outputs
Full Parallel Access for Loading
Buffered Control Inputs
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
tEPIC (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
54AC11533, 74AC11533
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS004 – D2957, JULY 1987 – REVISED APRIL 1993
54AC11533 . . . JT PACKAGE
74AC11533 . . . DW OR NT PACKAGE
(TOP VIEW)
1Q
2Q
3Q
4Q
GND
GND
GND
GND
5Q
6Q
7Q
8Q
1
2
3
4
5
6
7
8
9
10
11
12
24 OC
23 1D
22 2D
21 3D
20 4D
19 VCC
18 VCC
17 5D
16 6D
15 7D
14 8D
13 C
description
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight latches of the AC11533 are transparent
D-type latches. While the enable (C) is high, the
Q outputs will follow the complements of the (D)
inputs. When the output control OC is taken low,
the Q outputs will be latched. The AC11533 is
functionally equivalent to the AC11373 except for
having inverted outputs.
54AC11533 . . . FK PACKAGE
(TOP VIEW)
4 3 2 1 28 27 26
2D 5
25 7D
1D 6
24 8D
OC 7
23 C
NC 8
22 NC
1Q 9
21 8Q
2Q 10
20 7Q
3Q 11
19 6Q
12 13 14 15 16 17 18
A buffered output-control (OC) input can be used
to place the eight outputs in either a normal logic
NC – No internal connection
state (high or low logic levels) or a high-
impedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines significantly. The high-impedance third state and increased drive
provide the capability to drive the bus lines in a bus-organized system without need for interface or pull-up
components.
The output control (OC) does not affect the internal operations of the latches. Old data can be retained or new
data can be entered while the outputs are off.
The 54AC11533 is characterized for operation over the full military temperature range of – 55°C to 125°C. The
74AC11533 is characterized for operation from – 40°C to 85°C.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1993, Texas Instruments Incorporated
2–1


Texas Instruments (TI) Electronic Components Datasheet

54AC11533 Datasheet

OCTAL D-TYPE TRANSPARENT LATCHES

No Preview Available !

54AC11533, 74AC11533
OCTAL D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS004 – D2957, JULY 1987 – REVISED APRIL 1993
FUNCTION TABLE
(each latch)
INPUTS
OC C
OUTPUT
DQ
L HH L
LHLH
L L X Q0
HXXZ
logic symbol
logic diagram (positive logic)
24
OC
13
C
23
1D
22
2D
21
3D
20
4D
17
5D
16
6D
15
7D
14
8D
EN
C1
1D
1
1Q
2
2Q
3
3Q
4
4Q
9
5Q
10
6Q
11
7Q
12
8Q
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
24
OC
13
C
23
1D
22
2D
21
3D
20
4D
17
5D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
1
1Q
2
2Q
3
3Q
4
4Q
9
5Q
16
6D
C1
1D
10
6Q
15
7D
C1
1D
11
7Q
Pin numbers shown are for the DW, JT, and NT packages.
14
8D
C1
1D
12
8Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2–2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Part Number 54AC11533
Description OCTAL D-TYPE TRANSPARENT LATCHES
Maker Texas
Total Page 7 Pages
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