TH7301 Dual-Channel Programmable Low-Pass Filter
The IC is divided into I and Q channel signal
paths each consisting of an input stage, gyrator
4th order Butterworth low-pass filter, output stage
and feedback amplifier for an oscillator. A serial
interface is provided to allow the gain and cutoff
frequency to be programmed via a standard 3
wire interface. The digital cutoff frequency setting
is converted to a current by a digital-to-analog
converter. Internal bandgap references and
biasing blocks provide top level biasing on voltage
and current references for the complete device.
The device incorporates programmable attenua-
tion in the input stages to maintain filter linearity
and to provide overall gain control for the IC. The
attenuation can be programmed in coarse steps
of 3 dB with fine control of 0.5 dB in the input
transconductor of the gyrator filters. Internal
multiplexers and back to back followers allow
single-ended or differential input operation on both
I and Q signal paths.
4th order Butterworth filter
The filter architecture is based on a fully balanced
continuous time gyrator technique with 4th order
Butterworth response. Linear current programm-
able transconductance elements are used to
synthesise the two inductors and source and
termination impedance of the filter. A termination
to source impedance ratio of 2:1 is selected to
minimise output noise while maintaining a
realisable range of capacitor values.
The use of a differential architecture has three
distinct advantages. Firstly the ultimate noise
rejection is substantially better than that of the
unbalanced LC filter. Secondly differential drive
allows the use of a current programmable Gm
stage with very much greater signal handling. And
finally DC loading of the output is common mode
and does not lead to differential DC offsets. This
last point is especially important as the bias
current within the filter can become very low at
low cutoff frequencies.
The output stage is designed to carry out differential
to single ended conversion and provides the
capability of driving up to 15 pF of capacitive load.
The maintaining and limiting amplifier is used as
part of a phase shift oscillator circuit with the
gyrator Butterworth filter as the phase shift
element. The frequency of oscillation occurs at the
-3 dB frequency of the filter as the phase shift
through a 4th order Butterworth filter is 180
degrees at the -3 dB point. Voltage limiters are
integrated into the gyrator filters and limit the
differential voltage to 50 mVpp in order to ensure
that the transconductance elements remain in
their linear region of operation and hence the
expected inductance values are synthesised.
The filter cutoff frequency and gain are programm-
ed via a 3 wire serial interface bus. The interface
consists of the serial data clock (SCLK), serial
data input (SDATA) and a serial enable (SDEN).
The filter is programmed by asserting SDEN and
clocking the 8 bit serial data, MSB first, into the
shift register. The two most significant bits
represent the register address bits. The 6 LSB of
data are loaded into the relevant register on the
falling edge of SDEN.
The serial interface consists of: an 8 bit serial
input to parallel output (SIPO) register, three 6-bit
parallel load registers and register address
Once SDEN is asserted, data is clocked into the
SIPO on the positive edge of SCLK. When the
data is loaded, the two address bits are decoded
to determine which register should be updated.
The data is transfered to the register on the falling
edge of SDEN.
The serial interface does not contain a power on
reset, thus all three registers must be programmed
before reliable filter operation can be achieved.
The digital-to-analog converter is used to select
the filter cutoff frequency via a programmable
reference current. The fully companding DAC
divides the frequency range into 5 chords, each
with 128 equal frequency steps. The reference
current is programmed by an external resistor
placed between RDAC and Vee. The final output
is mirrored for the I and Q channels to provide
The chords are selected by a 3 bit word and the
frequency step by a 7 bit word. The companding
law is generated by adding the chord currents and
dividing the required chord into 128 step currents.
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