TM320240CGG
Description
FLM LP CP M Vadj VCC VSS VEE D0 D1 D2 D3 DISPOFF NC
H/L H L H L H/L -5.0V 0V H/L H/L H/L H/L H/L --
Indicates the beginning of each display cycle Data latch pulse Data shift clock pulse Alternate Signal For LCD Driver Operating voltage for LCD(variable) Supply voltage for logic and LCD(+) Ground Data Bit 0 Data Bit 1 Data Bit 2 Data Bit 3 H:Display on; L:Display off No Signal
-17.6V Supply voltage for LCD(-)
8/21
..
6.3 Interface Timing Chart 8080 family interface timing
Ta=-20 to 75 deg. C
Signal A0,CS WR,RD Symbol t AH8 t AW8 t CYC8 t CC t DS8 D0 to D7 t DH8 t ACC8 t OH8 Parameter Address hold time Address setup time System cycle time Strobe pulsewidth Data setup time Data hold time RD access time Output disable time VDD=4.5 to 5.5V min 10 0 See note. 120 120 5 10 max 50 50 VDD=2.7 to 5.5V min 10 0 See note. 150 120 5 10 max 80 55 Unit ns ns ns ns ns ns ns ns CL=100p F Condition
Note For memory control and system control mands: t CYC8 = 2 t C + t CC + t CEA + 75 > t ACV + 245...
