74HC237D Datasheet - Toshiba

3-to-8 Line Decoder/Latch

74HC237D Features

* (1) High speed: tpd = 12 ns (typ.) at VCC = 5 V (2) Low power dissipation: ICC = 4.0 µA (max) at Ta = 25  (3) Balanced propagation delays: tPLH ≈ tPHL (4) Wide operating voltage range: VCC(opr) = 2.0 V to 6.0 V 4. Packaging SOIC16 ©2016 Toshiba Corporation 1 Start of commercial production 2016-

74HC237D General Description

* 3-to-8 Line Decoder/Latch 2. General The 74HC237D is a high speed CMOS 3-to-8 DECODER ADDRESS LATCH fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. It is composed of a 3-bit in.

74HC237D Datasheet (223.66 KB)