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TC551001AFTL-70L - SILICON GATE CMOS STATIC RAM

Download the TC551001AFTL-70L datasheet PDF. This datasheet also covers the TC551001APL-70L variant, as both devices belong to the same silicon gate cmos static ram family and are provided as variant models within a single manufacturer datasheet.

General Description

The TC551 001APL is a 1,048,576 bit CMOS static random access memory organized as 131,072 words by 8 bits and operated from a single 5V power supply.

Key Features

  • with an operating current of 5mAlMHz (typ. ) and a minimum cycle time of 70ns. When CE1 is a logical high, or CE2 is low, the device is placed in a low power standby mode in which the standby current is 2~ typically. The TC551 001 APL has three control inputs. Chip enable inputs (CE1, CE2) allow for device selection and data retention control, while an output enable input (OE) provides fast memory access. The TC551001APL is suitable for use in microprocessor systems where high speed, low power, a.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC551001APL-70L-Toshiba.pdf) that lists specifications for multiple related part numbers.

Other Datasheets by Toshiba

Part Number Description
TC551001AFTL-70LT SILICON GATE CMOS STATIC RAM
TC551001AFTL-70LV SILICON GATE CMOS STATIC RAM
TC551001AFTL-70 SILICON GATE CMOS STATIC RAM
TC551001AFTL-10 SILICON GATE CMOS STATIC RAM
TC551001AFTL-10L SILICON GATE CMOS STATIC RAM
TC551001AFTL-10LT SILICON GATE CMOS STATIC RAM
TC551001AFTL-10LV SILICON GATE CMOS STATIC RAM
TC551001AFTL-85 SILICON GATE CMOS STATIC RAM
TC551001AFTL-85L SILICON GATE CMOS STATIC RAM
TC551001AFTL-85LT SILICON GATE CMOS STATIC RAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TOSHIBA SILICON GATE CMOS TC55100lAPL/AFL/AFIL/ATRL-70L/85L/10L(L1) 131,072 WORD x 8 BIT STATIC RAM Description The TC551 001APL is a 1,048,576 bit CMOS static random access memory organized as 131,072 words by 8 bits and operated from a single 5V power supply. Advanced circuit techniques provide both high speed and low power features with an operating current of 5mAlMHz (typ.) and a minimum cycle time of 70ns. When CE1 is a logical high, or CE2 is low, the device is placed in a low power standby mode in which the standby current is 2~ typically. The TC551 001 APL has three control inputs. Chip enable inputs (CE1, CE2) allow for device selection and data retention control, while an output enable input (OE) provides fast memory access.