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TC58BVG1S3HTAI0 - 2 GBIT (256M x 8 BIT) CMOS NAND E2PROM

General Description

The TC58BVG1S3HTAI0 is a single 3.3V 2 Gbit (2,214,592,512 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 64 pages × 2048blocks.

Key Features

  • Organization x8 Memory cell array 2112 × 128K × 8 Register 2112 × 8 Page size 2112 bytes Block size (128K + 4K) bytes.
  • Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Read, Multi Page Program, Multi Block Erase, ECC Status Read.
  • Mode control Serial input/output Command control.
  • Number of valid blocks Min 2008 blocks Max 2048 blocks.
  • Power supply VCC = 2.7V to 3.6V.
  • Access time Cell arr.

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Datasheet Details

Part number TC58BVG1S3HTAI0
Manufacturer Toshiba
File Size 683.01 KB
Description 2 GBIT (256M x 8 BIT) CMOS NAND E2PROM
Datasheet download datasheet TC58BVG1S3HTAI0 Datasheet

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Part Number Description
TC58BVG1S3HTA00 2 GBIT (256M x 8 BIT) CMOS NAND E2PROM
TC58BVG1S3HBAI4 2 GBIT (256M x 8 BIT) CMOS NAND E2PROM
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Full PDF Text Transcription (Reference)

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TC58BVG1S3HTAI0 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 GBIT (256M × 8 BIT) CMOS NAND E2PROM DESCRIPTION The TC58BVG1S3HTAI0 is a single 3.3V 2 Gbit (2,214,592,512 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 64 pages × 2048blocks. The device has a 2112-byte static register which allows program and read data to be transferred between the register and the memory cell array in 2112-bytes increments. The Erase operation is implemented in a single block unit (128 Kbytes + 4 Kbytes: 2112 bytes × 64 pages). The TC58BVG1S3HTAI0 is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs.