TC58FVM6(T/B)2A(FT/XB)65
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
64MBIT (8M × 8 BITS/4M × 16 BITS) CMOS FLASH MEMORY
DESCRIPTION
The TC58FVM6T2A/B2A is a 67108864-bit, 3.0-V read-only electrically erasable and programmable flash
memory organized as 8388608 words × 8 bits or as 4194304 words × 16 bits. The TC58FVM6T2A/B2A features
commands for Read, Program and Erase operations to allow easy interfacing with microprocessors. The commands
are based on the JEDEC standard. The Program and Erase operations are automatically executed in the chip. The
TC58FVM6T2A/B2A also features a Simultaneous Read/Write operation so that data can be read during a Write or
Erase operation.
FEATURES
• Power supply voltage
• Block erase architecture
VDD = 2.3 V~3.6 V
8 × 8 Kbytes/127 × 64 Kbytes
• Operating temperature
• Boot block architecture
Ta = −40°C~85°C
TC58FVM6T2A: top boot block
• Organization
TC58FVM6B2A: bottom boot block
8M × 8 bits/4M × 16 bits
• Mode control
• Functions
Compatible with JEDEC standard commands
Simultaneous Read/Write
Page Read
• Erase/Program cycles
105 cycles typ.
Auto Program, Auto Page Program
• Access Time (Random/Page)
Auto Block Erase, Auto Chip Erase
Fast Program Mode/Acceleration Mode
VDD
CL = 30 pF
CL = 100 pF
Program Suspend/Resume
2.7~3.6 V
65 ns/25 ns
70 ns/30 ns
Erase Suspend/Resume
2.3~3.6 V
70 ns/30 ns
75 ns/35 ns
data polling/Toggle bit
block protection, boot block protection
Automatic Sleep, support for hidden ROM area
common flash memory interface (CFI)
Byte/Word Modes
•
Power consumption
10 µA (Standby)
15 mA (Program/Erase operation)
55 mA (Random Read operation)
11 mA (Address Increment Read operation)
5 mA (Page Read operation)
• Package
TC58FVM6**AFT:
TSOPI48-P-1220-0.50 (weight: 0.51 g)
TC58FVM6**AXB:
P-TFBGA56-0710-0.80AZ (weight: 0.125 g)
2003-01-29 1/61
