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TC58NVG1S3HTA00 - 2 GBIT (256M x 8 BIT) CMOS NAND E2PROM

General Description

The TC58NVG1S3HTA00 is a single 3.3V 2 Gbit (2,281,701,376 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048  128) bytes  64 pages  2048blocks.

Key Features

  • Organization Memory cell array Register Page size Block size x8 2176  128K  8 2176  8 2176 bytes (128K  8K) bytes.
  • Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read.
  • Mode control Serial input/output Command control.
  • Number of valid blocks Min 2008 blocks Max 2048 blocks.
  • Power supply VCC  2.7V to 3.6V.
  • Access time Cell array to register 25 s max Seria.

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Datasheet Details

Part number TC58NVG1S3HTA00
Manufacturer Toshiba
File Size 706.98 KB
Description 2 GBIT (256M x 8 BIT) CMOS NAND E2PROM
Datasheet download datasheet TC58NVG1S3HTA00 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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TC58NVG1S3HTA00 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 GBIT (256M  8 BIT) CMOS NAND E2PROM DESCRIPTION The TC58NVG1S3HTA00 is a single 3.3V 2 Gbit (2,281,701,376 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048  128) bytes  64 pages  2048blocks. The device has two 2176-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 2176-byte increments. The Erase operation is implemented in a single block unit (128 Kbytes  8 Kbytes: 2176 bytes  64 pages). The TC58NVG1S3HTA00 is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs.