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TC74AC109F - Dual J-K Flip-Flop

This page provides the datasheet information for the TC74AC109F, a member of the TC74AC109P Dual J-K Flip-Flop family.

Datasheet Summary

Features

  • High speed: fmax = 200 MHz (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C.
  • High noise immunity: VNIH = VNIL = 28% VCC (min).
  • Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω transmission lines.
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Wide operating voltage range: VCC (opr) = 2 to 5.5 V.
  • Pin and function compatible with 74F109 Pin Assignment TC74AC109P TC74AC10.

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Datasheet preview – TC74AC109F

Datasheet Details

Part number TC74AC109F
Manufacturer Toshiba
File Size 284.74 KB
Description Dual J-K Flip-Flop
Datasheet download datasheet TC74AC109F Datasheet
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Full PDF Text Transcription

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TC74AC109P/F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC109P, TC74AC109F Dual J-K Flip Flop with Preset and Clear The TC74AC109 is an advanced high speed CMOS DUAL J- K FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. In accordance with the logic level given J and K input this device changes state on positive going transition of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low logic level on the corresponding input. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features • High speed: fmax = 200 MHz (typ.
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