TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
Dual J-K Flip Flop with Preset and Clear
The TC74ACT112 is an advanced high speed CMOS DUAL J-K
FLIP FLOP fabricated with silicon gate and double-layer metal
wiring C2MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
This device may be used as a level converter for interfacing
TTL or NMOS to High Speed CMOS. The inputs are compatible
with TTL, NMOS and CMOS output voltage levels.
In accordance with the logic level given J and K input this
device changes state on negative going transition of the clock
pulse. CLEAR and PRESET are independent of the clock and
accomplished by a low logic level on the corresponding input.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
• High speed: fmax = 175 MHz (typ.) at VCC = 5 V
• Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
• Compatible with TTL outputs: VIL = 0.8 V (max)
VIH = 2.0 V (min)
• Symmetrical output impedance: |IOH| = IOL = 24 mA (min)
Capability of driving 50 Ω
• Balanced propagation delays: tpLH ∼− tpHL
• Pin and function compatible with 74F112
: 1.00 g (typ.)
: 0.18 g (typ.)
Start of commercial production