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TC74HC107AP Datasheet Dual J-K Flip-Flop

Manufacturer: Toshiba

Download the TC74HC107AP datasheet PDF. This datasheet also includes the TC74HC107 variant, as both parts are published together in a single manufacturer document.

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Note: The manufacturer provides a single datasheet file (TC74HC107_Toshiba.pdf) that lists specifications for multiple related part numbers.

Overview

TC74HC107AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC107AP, TC74HC107AF Dual J-K Flip Flop with Clear The TC74HC107A is a high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate C2MOS technology.

It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation.

In accordance with the logic levels applied to the J and K inputs, the outputs change state on the negative going transition of the clock pulse.

Key Features

  • High speed: fmax = 75 MHz (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 2 μA (max) at Ta = 25°C.
  • High noise immunity: VNIH = VNIL = 28% VCC (min).
  • Output drive capability: 10 LSTTL loads.
  • Symmetrical output impedance: |IOH| = IOL = 4 mA (min).
  • Balanced propagation delays: tpLH ∼.

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