TC74HC109AFN - DUAL J-K FLIP-FLOP
It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation.
In accordance with the logic levels applied to the J and K inputs, the outputs change state on the positive going transition of the clock pulse.
C
TC74HC109AFN Features
* High speed: fmax = 63 MHz (typ.) at VCC = 5 V
* Low power dissipation: ICC = 2 μA (max) at Ta = 25°C
* High noise immunity: VNIH = VNIL = 28% VCC (min)
* Output drive capability: 10 LSTTL loads
* Symmetrical output impedance: |IOH| = IOL = 4 mA (min)