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TC74HC10AP - Triple 3-Input NAND Gate

This page provides the datasheet information for the TC74HC10AP, a member of the TC74HC10 Triple 3-Input NAND Gate family.

Datasheet Summary

Features

  • High speed: tpd = 6 ns (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 1 μA (max) at Ta = 25°C.
  • High noise immunity: VNIH = VNIL = 28% VCC (min).
  • Output drive capability: 10 LSTTL loads.
  • Symmetrical output impedance: |IOH| = IOL = 4 mA (min).
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Wide operating voltage range: VCC (opr) = 2 to 6 V.
  • Pin and function compatible with 74LS10 Pin Assignment T.

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Datasheet preview – TC74HC10AP

Datasheet Details

Part number TC74HC10AP
Manufacturer Toshiba
File Size 203.35 KB
Description Triple 3-Input NAND Gate
Datasheet download datasheet TC74HC10AP Datasheet
Additional preview pages of the TC74HC10AP datasheet.

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Full PDF Text Transcription

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TC74HC10AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC10AP, TC74HC10AF Triple 3-Input NAND Gate The TC74HC10A is a high speed CMOS 3-INPUT NAND GATE fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The internal circuit is composed of 3 stages including buffer output, which provide high noise immunity and stable output. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features • High speed: tpd = 6 ns (typ.
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