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TC74HC125AP - Quad Bus Buffer

Features

  • High speed: tpd = 10 ns (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C.
  • High noise immunity: VNIH = VNIL = 28% VCC (min).
  • Output drive capability: 15 LSTTL loads.
  • Symmetrical output impedance: |IOH| = IOL = 6 mA (min).
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Wide operating voltage range: VCC (opr) = 2 to 6 V.
  • Pin and function compatible with 74LS125/126 TC74HC125AP, TC74HC126AP TC74HC1.

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Datasheet preview – TC74HC125AP

Datasheet Details

Part number TC74HC125AP
Manufacturer Toshiba
File Size 214.82 KB
Description Quad Bus Buffer
Datasheet download datasheet TC74HC125AP Datasheet
Additional preview pages of the TC74HC125AP datasheet.

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Full PDF Text Transcription

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TC74HC125AP/AF,126AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC125AP, TC74HC125AF TC74HC126AP, TC74HC126AF TC74HC125AP/AF TC74HC126AP/AF Quad Bus Buffer Quad Bus Buffer The TC74HC125A/126A are high speed CMOS QUAD BUS BUFFERs fabricated with silicon gate C2MOS technology. They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The TC74HC125A requires the 3-state control input G to be set high to place the output into the high impedance state, whereas the TC74HC126A requires the control input to be set low to place the output into high impedance. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features • High speed: tpd = 10 ns (typ.
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