TC74HC151AFN Overview
It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. One of eight date input signals (D0-D7) is selected by decoding of the three-bit address input (A, B, C). The selected data appears on two outputs:.
TC74HC151AFN Key Features
- High speed: tpd = 15 ns (typ.) at VCC = 5 V
- Low power dissipation: ICC = 4 μA (max) at Ta = 25