TC74HC251AF Overview
It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. One of eight date input signals (D0-D7) is selected by decoding of the address input (A, B, C). The selected data appears on two outputs;.
TC74HC251AF Key Features
- High speed: tpd = 15 ns (typ.) at VCC = 5 V
- Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
- High noise immunity: VNIH = VNIL = 28% VCC (min)
- Output drive capability: 10 LSTTL loads
- Symmetrical output impedance: |IOH| = IOL = 4 mA (min)
- Balanced pro