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Toshiba Electronic Components Datasheet

TC74HC259AF Datasheet

8-Bit Addressable Latch

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TC74HC259AP/AF
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HC259AP, TC74HC259AF
8-Bit Addressable Latch
The TC74HC259A is a high speed CMOS ADDRESSABLE
LATCH fabricated with silicon gate C2MOS technology.
It achieve the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
The respective bits are controlled by address inputs A, B, and
C. When CLEAR input is held high and enable input G is held
low, the data is written into the bit selected by address inputs,
the other bit hold their previous conditions.
When both CLEAR and G held high, writing of all bits is
inhibited regardless of adress inputs, and their previous
condition are held. When CLEAR is held low and G is held
high, all bits are resent to low regardless of the other inputs.
When both of CLEAR and G held low, all bits which isn’t
selected by adress inputs are resent to low.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
High speed: tpd = 15 ns (typ.) at VCC = 5 V
Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
High noise immunity: VNIH = VNIL = 28% VCC (min)
Output drive capability: 10 LSTTL loads
Symmetrical output impedance: |IOH| = IOL = 4 mA (min)
Balanced propagation delays: tpLH ∼− tpHL
Wide operating voltage range: VCC (opr) = 2 to 6 V
Pin and function compatible with 74LS259
Pin Assignment
TC74HC259AP
TC74HC259AF
Weight
DIP16-P-300-2.54A
SOP16-P-300-1.27A
: 1.00 g (typ.)
: 0.18 g (typ.)
Start of commercial production
1988-05
1 2014-03-01


Toshiba Electronic Components Datasheet

TC74HC259AF Datasheet

8-Bit Addressable Latch

No Preview Available !

IEC Logic Symbol
TC74HC259AP/AF
Truth Table
Inputs
CLEAR G
HL
HH
LL
LH
Output of
Addressed
Latch
D
QiO
D
L
Each Other
Output
Function
QiO Addressable Latch
QiO Memory
L 8-Line Demultriplexer
L Clear All Bits to “L”
Select Inputs
CBA
LLL
L LH
LHL
L HH
HL L
HLH
HH L
HHH
Latch Addressed
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D: The level at the data input.
QiO: The level before the indicared steady-state input conditions were established (i = 0, 1, .... 7)
2 2014-03-01


Part Number TC74HC259AF
Description 8-Bit Addressable Latch
Maker Toshiba
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TC74HC259AF Datasheet PDF





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