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Toshiba Electronic Components Datasheet

TC74HC299AP Datasheet

8-Bit PIPO Shift Register

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TC74HC299AP/AF
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HC299AP, TC74HC299AF
8-Bit PIPO Shift Register with Asynchronous Clear
The TC74HC299A is a high speed CMOS 8-BIT PIPO SHIFT
REGISTER fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
It has four modes (HOLD, SHIFT LEFT, SHIFT RIGHT and
LOAD DATA) controlled by the two selection inputs (S0, S1).
When one or both enable ( G1 , G2 ) are high, the eight I/O
outputs are forced to the high-impedance state; however,
sequential operation or clearing of the register is not affected.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
TC74HC299AP
TC74HC299AF
Features (Note 1) (Note 2)
High speed: fmax = 42 MHz (typ.) at VCC = 5 V
Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
High noise immunity: VNIH = VNIL = 28% VCC (min)
Outputs drive capability
: 15 LSTTL loads for QA to QH
10 LSTTL loads for QA’, QH’
Symmetrical output impedance
: |IOH| = IOL = 6 mA (min) For QA to QH
|IOH| = IOL = 4 mA (min) For QA’, QH’
Balanced propagation delays: tpLH ∼− tpHL
Wide operating voltage range: VCC (opr) = 2 to 6 V
Pin and function compatible with 74LS299
Weight
DlP20-P-300-2.54A
SOP20-P-300-1.27A
: 1.30 g (typ.)
: 0.22 g (typ.)
Note 1: Do not apply a signal to any bus terminal when it is in the output mode. Damage may result.
Note 2: All floating (high impedance) bus terminals must have their input levels fixed by means of pull up or pull
down resistors.
Pin Assignment
Start of commercial production
1987-10
1
2014-03-01


Toshiba Electronic Components Datasheet

TC74HC299AP Datasheet

8-Bit PIPO Shift Register

No Preview Available !

IEC Logic Symbol
TC74HC299AP/AF
Truth Table
Mode
CLR
Z
L
L
CLR
L
Hold H
Shift H
Right H
Shift H
Left H
Load H
Function
Select
S1 S0
H
H
L
X
X
L
L
L
L
H
L
H
H
L
H
L
H
H
Inputs
Outputs
Control
Clock
G1
(Note)
G2
(Note)
CK
X
X
X
L
L
X
L
L
X
L
L
X
L
L
L
L
L
L
L
L
X
X
Serial
SL SR
X
X
X
X
X
X
X
X
X
H
X
L
H
X
L
X
X
X
Inputs
/Outputs
Outputs
A/QA H/QH QA’ QH’
Z
L
L
QA0
H
L
QBn
QBn
a
Z
L
L
QH0
QGn
QGn
H
L
h
L
L
L
QA0
H
L
QBn
QBn
a
L
L
L
QH0
QGn
QGn
H
L
h
Note: When one or both output controls are high, the eight input/output terminals are in the high-impedance state;
however sequential or clearing of the register is not affected.
Z: High impedance
Qn0: The level of Qn before the indicated steady-state input conditions were established.
Qnn: The level of Qn before the most recent active transition indicated by or .
a, h: The level of the steady-state inputs A, H, respectively.
X: Don’t care.
2
2014-03-01


Part Number TC74HC299AP
Description 8-Bit PIPO Shift Register
Maker Toshiba
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TC74HC299AP Datasheet PDF






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