TC74HC40102AP - Dual BCD Programmable Down Counter

Product Overview

Toshiba

Datasheet Details

Part number	TC74HC40102AP
Manufacturer	Toshiba
File Size	426.07 KB
Description	Dual BCD Programmable Down Counter
Datasheet	TC74HC40102AP Datasheet
Additional preview pages of the TC74HC40102AP datasheet.

Product details

Description

Count Inhibit Count is inhibited regardless of other inputs.Regular Count Down count on the rising edge of CK Synchronous Preset Input data is preset on the rising edge of CK Asynchronous Preset Input data is asynchronously preset to CK Clear Counter is set to maximum count.X: Don’t care Maximum count: TC74HC40102A “99”, TC74HC40103A “255” 2 2014-03-01 Timing Chart TC74HC40102,40103AP/AF 3 2014-03-01 System Diagram TC74HC40102A TC74HC40102,40103AP/AF TC74HC40103A 4 2014-03-0

Features

High speed: fmax 40 MHz (typ. ) at VCC = 5 V.
Low power dissipation: ICC = 4 μA (max) at Ta = 25°C.
High noise immunity: VNIH = VNIL = 28% VCC (min).
Output drive capability: 10 LSTTL loads.
Symmetrical output impedance: |IOH| = IOL = 4 mA (min).
Balanced propagation delays: tpLH ∼.
tpHL.
Wide operating voltage range: VCC (opr) = 2 to 6 V.
Pin and function compatible with 40102B, 40103B Weight DIP16-P-300-2.54A SOP1.

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Published: Jan 23, 2021 |