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TC74VHCT9126AFK - 5-bit Universal Schmitt Buffer

Download the TC74VHCT9126AFK datasheet PDF. This datasheet also covers the TC74VHCT9125AFK variant, as both devices belong to the same 5-bit universal schmitt buffer family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • High speed: tpd = 6.6 ns (typ. ) (VCC = 5 V).
  • Low supply current: ICC = 2 μA (max) (Ta = 25°C).
  • Compatible with TTL inputs VIL = 0.5 V (max) VIH = 2.1 V (min).
  • Power down protection is provided on all inputs.
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Input terminals are at the opposite side of Output terminals © 2019 1 Toshiba Electronic Devices & Storage Corporation Start of commercial production 2010-07 2019-01-31 Pin Assignment TC74VHCT9125,9126AF.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74VHCT9125AFK-Toshiba.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Toshiba

Part Number Description
TC74VHCT9125AFK 5-bit Universal Schmitt Buffer
TC74VHCT9273FK Octal D-Type Flip-Flop
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TC74VHCT00AF Quad 2-Input NAND Gate

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC74VHCT9125,9126AFK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHCT9125AFK TC74VHCT9126AFK TC74VHCT9125AFK 5-bit Universal Schmitt Buffer with 3-State Outputs TC74VHCT9126AFK 5-bit Universal Schmitt Buffer with 3-State Outputs TC74VHCT9125AFK, TC74VHCT9126AFK The TC74VHCT9125A/9126A are an ultra-high-speed 5-bit Schmitt buffer fabricated using silicon-gate CMOS technology. The TC74VHCT9125A/9126A combines low power consumption of CMOS with Schottky TTL speeds. The input voltage are compatible with TTL output voltage. This device may be used as a level converter for interfacing 3.3 V to 5 V system. Y1 to Y4 outputs can be put in the high-impedance state by placing a logic HIGH on the Enable ( G ) input. The CONT input determines the logical inversion of data.