TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHCT9125AFK 5-bit Universal Schmitt Buffer with 3-State Outputs
TC74VHCT9126AFK 5-bit Universal Schmitt Buffer with 3-State Outputs
The TC74VHCT9125A/9126A are an ultra-high-speed 5-bit Schmitt buffer
fabricated using silicon-gate CMOS technology.
The TC74VHCT9125A/9126A combines low power consumption of CMOS
with Schottky TTL speeds.
The input voltage are compatible with TTL output voltage.
This device may be used as a level converter for interfacing 3.3 V to 5 V
Y1 to Y4 outputs can be put in the high-impedance state by placing a logic
HIGH on the Enable ( G ) input. The CONT input determines the logical
inversion of data.A logic LOW on the CONT input configures the
: 0.02 g (typ.)
TC74VHC9125A/9126A as an inverter; a logic HIGH on the CONT input
configures the TC74VHCT9125A/9126A as a buffer.
TC74VHCT9125A Y5 output is an inverting type, and the TC74VHCT9126A Y5 output is a non-inverting type.
All the inputs have hysteresis between the positive-going and negative-going thresholds. Thus the TC74VHC9125A/9126A are
capable of squaring up transitions of slowly changing input signals and provides an improved noise immunity.
Input protection and output circuit ensure that 0 to 5.5 V can be applied to the input and output (Note) pins without regard to the
supply voltage. These structure prevents device destruction due to mismatched supply and input/output voltages such as battery
back up, etc.
Note: Output in off-state
High speed: tpd = 6.6 ns (typ.) (VCC = 5 V)
Low supply current: ICC = 2 μA (max) (Ta = 25°C)
Compatible with TTL inputs
VIL = 0.5 V (max)
VIH = 2.1 V (min)
Power down protection is provided on all inputs.
Balanced propagation delays: tpLH ∼− tpHL
Input terminals are at the opposite side of Output terminals
Toshiba Electronic Devices & Storage Corporation
Start of commercial production